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| Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER FEATURES * Two differential LVHSTL compatible outputs * One differential CLK, nCLK input pair * CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL * Maximum output frequency: 700MHz * Translates any single-ended input signal to LVHSTL levels with resistor bias on nCLK input * Output skew: 30ps (maximum) * Part-to-part skew: 250ps (maximum) * Propagation delay: 1.3ns (maximum) * Output duty cycle: 49% - 51% up to 266.6MHz * VOH = 1.15V (maximum) * 3.3V operating supply * -40C to 85C ambient operating temperature * Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION The ICS85211BI-03 is a low skew, high perforIC S mance 1-to-2 Differential-to-LVHSTL Fanout HiPerClockSTM Buffer and a member of the HiPerClockSTM family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85211BI-03 is characterized to operate from a 3.3V power supply. Guaranteed output and par t-to-par t skew characteristics make the ICS85211BI-03 ideal for those clock distribution applications demanding well defined performance and repeatability. BLOCK DIAGRAM Q0 nQ0 Q1 nQ1 PIN ASSIGNMENT Q0 nQ0 Q1 nQ1 1 2 3 4 8 7 6 5 VDD CLK nCLK GND CLK nCLK ICS85211BI-03 8-Lead SOIC 3.90mm x 4.90mm x 1.37mm package body M Package Top View 85211BMI-03 www.icst.com/products/hiperclocks.html 1 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Type Output Output Power Input Input Power Pullup/ Pulldown Pullup Description Differential output pair. LVHSTL interface levels. Differential output pair. LVHSTL interface levels. Power supply ground. Inver ting differential clock input. VDD/2 default when left floating. Non-inver ting differential clock input. Positive supply pin. TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 4 5 6 7 8 Name Q0, nQ0 Q1, nQ1 GND nCLK CLK VDD NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF K K TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs CLK 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nCLK 0 1 Biased; NOTE 1 Biased; NOTE 1 0 1 Q0, Q1 LOW HIGH LOW HIGH HIGH LOW Outputs nQ0, nQ1 HIGH LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels". 85211BMI-03 www.icst.com/products/hiperclocks.html 2 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 4.6V -0.5V to VDD + 0.5 V 50mA 100mA 112.7C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol VDD IDD Parameter Power Supply Voltage Power Supply Current Test Conditions Minimum 3.135 Typical 3.3 Maximum 3.465 55 Units V mA TABLE 4B. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol IIH IIL VPP Parameter Input High Current Input Low Current nCLK CLK nCLK CLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -150 -5 1.3 VDD - 0.85 Minimum Typical Maximum 150 150 Units A A A A V V Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; 0.5 VCMR NOTE 1, 2 NOTE 1: For single ended applications the maximum input voltage for CLK and nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. TABLE 4C. LVHSTL DC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol Parameter VOH VOL VSWING Output High Voltage Output Low Voltage Peak-to-Peak Output Voltage Swing Test Conditions Minimum 0.7 0 0.3 0.65 Typical Maximum 1.15 0.4 1.15 Units V V V 85211BMI-03 www.icst.com/products/hiperclocks.html 3 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Test Conditions 600MHz Minimum 0.9 Typical Maximum 700 1.3 30 250 20% to 80% 185 47 450 53 Units MHz ns ps ps ps % TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, TA = -40C TO 85C Symbol fMAX tPD t sk(o) t sk(pp) tR / tF o dc Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Output Rise/Fall Time Output Duty Cycle 266.6MHz 49 51 % All parameters measured at 600MHz unless noted otherwise. The cycle-to-cycle jitter on the input will equal the jitter on the output. The par t does not add jitter. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. 85211BMI-03 www.icst.com/products/hiperclocks.html 4 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 3.3V5% V DD Qx SCOPE V DD nCLK LVHSTL nQx V PP Cross Points V CMR CLK GND GND 0V 3.3V OUTPUT LOAD AC TEST CIRCUIT nQx Qx nQy Qy tsk(o) DIFFERENTIAL INPUT LEVEL Qx PART 1 nQx Qy PART 2 nQy tsk(pp) OUTPUT SKEW PART-TO-PART SKEW nCLK 80% 80% VSW I N G CLK nQ0, nQ1 Q0, Q1 tPD Clock Outputs 20% tR tF 20% OUTPUT RISE/FALL TIME nQ0, nQ1 Q0, Q1 PROPAGATION DELAY t PW t PERIOD odc = t PW t PERIOD x 100% OUTPUT DUTY CYCLE/PULSE WIDTH PERIOD 85211BMI-03 www.icst.com/products/hiperclocks.html 5 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: LVHSTL OUTPUT All unused LVHSTL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. 85211BMI-03 www.icst.com/products/hiperclocks.html 6 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50 R3 50 LVPECL Zo = 50 Ohm CLK nCLK HiPerClockS Input HiPerClockS Input R1 50 R2 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125 3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm CLK nCLK Receiv er FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input R5 100 - 200 R6 100 - 200 R1 84 R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 85211BMI-03 www.icst.com/products/hiperclocks.html 7 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER LVHSTL driver. The decoupling capacitors should be physically located near the power pin. Zo = 50 Ohm SCHEMATIC EXAMPLE Figure 3 shows a schematic example of ICS85211BI-03. In this example, the input is driven by an ICS HiPerClockS 1.8V Zo = 50 Ohm 5 6 7 8 U1 GND nCLK CLK VDD nQ1 Q1 nQ0 Q0 4 3 2 1 Zo = 50 Ohm - + R1 50 R2 50 LVHSTL Input Zo = 50 Ohm LVHSTL ICS HiPerClockS LVHSTL Driv er R6 50 R5 50 VDD=3.3V C1 0.1u ICS85211BMI-03 Zo = 50 Ohm Zo = 50 Ohm + Unused Output Can Be Floated R3 50 R4 50 LVHSTL Input FIGURE 3. ICS85211BI-03 LVHSTL BUFFER SCHEMATIC EXAMPLE 85211BMI-03 www.icst.com/products/hiperclocks.html 8 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS85211BI-03. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85211BI-03 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. * * Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 55mA = 190.6mW Power (outputs)MAX = 77.76mW/Loaded Output pair If all outputs are loaded, the total power is 2 * 77.76mW = 155.52mW Total Power_MAX (3.465V, with all outputs switching) = 190.6mW + 155.52mW = 346.12mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C. The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 103.3C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 0.346W * 103.3C/W = 120.7C. This is below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 6. THERMAL RESISTANCE JA FOR 8-PIN SOIC, FORCED CONVECTION JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. 85211BMI-03 www.icst.com/products/hiperclocks.html 9 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVHSTL output driver circuit and termination are shown in Figure 4. VDD Q1 VOUT RL 50 FIGURE 4. LVHSTL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50 load. Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = (VOH_MAX /R ) * (VDD_MAX - V L L ) OH_MAX Pd_L = (VOL_MAX /R ) * (VDD_MAX - VOL_MAX) Pd_H = (1.15V/50) * (3.465V - 1.15V) = 53.24mW Pd_L = (0.4V (50) * (3.465V - 0.4V) = 24.52mW Total Power Dissipation per output pair = Pd_H + Pd_L = 77.76mW 85211BMI-03 www.icst.com/products/hiperclocks.html 10 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER RELIABILITY INFORMATION TABLE 7. JAVS. AIR FLOW TABLE FOR 8 LEAD SOIC JA by Velocity (Linear Feet per Minute) 0 Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 153.3C/W 112.7C/W 200 128.5C/W 103.3C/W 500 115.5C/W 97.1C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS85211BI-03 is: 472 85211BMI-03 www.icst.com/products/hiperclocks.html 11 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER 8 LEAD SOIC PACKAGE OUTLINE - M SUFFIX FOR TABLE 8. PACKAGE DIMENSIONS SYMBOL N A A1 B C D E e H h L 5.80 0.25 0.40 0 1.35 0.10 0.33 0.19 4.80 3.80 1.27 BASIC 6.20 0.50 1.27 8 Millimeters MINIMUN 8 1.75 0.25 0.51 0.25 5.00 4.00 MAXIMUM Reference Document: JEDEC Publication 95, MS-012 85211BMI-03 www.icst.com/products/hiperclocks.html 12 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER Marking 211BMI03 211BMI03 211BI03L 211BI03L Package 8 lead SOIC 8 lead SOIC 8 lead "Lead-Free" SOIC 8 lead "Lead-Free" SOIC Shipping Packaging tube 2500 tape & reel tube 2500 tape & reel Temperature -40C to 85C -40C to 85C -40C to 85C -40C to 85C TABLE 9. ORDERING INFORMATION Part/Order Number ICS85211BMI-03 ICS85211BMI-03T ICS85211BMI-03LN ICS85211BMI-03LNT NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 85211BMI-03 www.icst.com/products/hiperclocks.html 13 REV. B NOVEMBER 15, 2005 Integrated Circuit Systems, Inc. ICS85211BI-03 LOW SKEW, 1-TO-2 DIFFERENTIAL-TO-LVHSTL FANOUT BUFFER REVISION HISTORY SHEET Description of Change Power Supply Table - changed IDD max. from 50mA to 55mA. Power Considerations - changed the IDD limit from 50mA to 55mA to reflect Table 4A. Recalculated Power Dissipation and Junction Temperature formulas. Features Section - add Lead-Free bullet. Updated Differential Clock Input Interface section. Added Lead-Free par t number to Ordering Information table. Ordering Information Table - corrected Lead-Free P/N from "LF" to "LN". Ordering Information Table - corrected marking to read 211BMI02". Added Recommendations for Unused Input and Output Pins. Corrected Power Considerations, Power Dissipation calculation. Ordering Information Table - added lead-free note. Date 10/15/03 Rev B Table T4A Page 3 8 1 7 12 12 12 6 9-10 13 B B B B T9 T8 T8 T8 9/14/04 10/11/04 10/18/04 11/15/05 85211BMI-03 www.icst.com/products/hiperclocks.html 14 REV. B NOVEMBER 15, 2005 |
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